A processor (hereinafter also referred to as a CPU (central processing unit)) is typically implemented on an integrated circuit ("IC") and is coupled to various external resources (devices) by a system bus. Such external devices may include flash memory devices, read-only memory ("ROM") devices, random access memory ("RAM") devices, dynamic random access memory ("DRAM") devices, universal asynchronous receiver/transmitter ("UART") devices, application specific integrated circuits ("ASIC"), timer devices, other microprocessors, direct memory access ("DMA") channels, hard disks, tape drives, CD-ROMs, network communications adapters, user interfaces, and display devices. These various devices are the eyes, ears, mouth, arms, and legs to the processor's brain. In other words, a processor alone, with no means of external communication, is practically a worthless hunk of silicon.
The system bus, which couples all of these various external devices to the processor, is typically a plurality of transmission lines operating in parallel. It could be said that the equivalent of the bus in the human body is the central nervous system.
Since all or most of the transmission lines of the system bus are coupled to the processor and to all of the various external devices, an addressing scheme is needed so that only the intended destination of a set of data or instructions transmitted from the processor or from one of the external devices is received by that intended destination. The set of addresses for a particular system can be parsed into a plurality of address spaces. An address space is made up of one or more addresses. A particular address space may be dedicated to a particular external device. The address spaces are generally indicated by asserting a chip select signal to a specific device.
When the processor desires to read information located at a particular address space, or desires to write information to a particular address space, a bus protocol is initiated between the processor and the external device corresponding to the particular address space. This bus protocol typically includes an alert signal to the external device that a read or write access is about to occur, and a notification to the external device to indicate whether or not the access is a read or a write. This bus protocol is produced by a system bus controller located in the processor and is coupled between the core circuitry of the processor (hereinafter referred to also as the "core") and the system bus. The system bus controller acts as an interface between read and write requests received from the core and the system bus.
A problem occurs when data processing systems are configured using a processor and external devices produced by different manufacturers, since there is no general standard bus protocol uniformly implemented by all manufacturers. Thus, different external devices may require different bus protocol signals.
For example, different types of external memory devices (one type of external device) may require differing values of read/write access signals in order to interface correctly with the processor. Prior art processors are rigid in that they produce only one value for the read/write access signal. If this signal is asserted high by the processor for a write access to an external device, but the external device requires that this received signal be asserted low, then the processor and the external device will not be able to interface correctly. For example, the external device may operate as if the write access from the processor is a read access.
Prior art solutions to this problem have been the implementation of additional external logic circuitry implemented on the system bus between the processor and the external device. Since such external logic circuitry requires space (increases cost) on an IC or a printed circuit board ("PCB") and increases associated overhead costs, it is desirable not to include such external logic circuitry. The external logic circuitry typically introduces additional time delay into the system bus access, thereby lowering the overall system performance. Therefore, there is a need in the art for a technique for interfacing a processor to one or more external devices, regarding read/write access signals, without requiring additional external logic circuitry. In other words, what is needed in the art is a "glueless" interface between such a processor and one or more external devices.